The average x86 instruction is 3-4 bytes long in integer code (our test with 8 byte NOPs is more applicable to very AVX-heavy code). Past L1, all CPUs here can read 16 bytes/cycle from L2. However, this is largely mitigated by Golden Cove’s higher bandwidth L1 instruction cache. In fact, the shape of Golden Cove’s curve is similar to Skylake’s, suggesting a large number of uop cache misses with just over 1024 NOPs (8 KB) in the loop. Strangely, we’re not able to see Golden Cove’s larger uop cache with our test. For Ice Lake, it’s 40 bytes/cycle, and for Skylake, it’s 32 bytes/cycle. Ideal (core width limited) instruction bandwidth for GLC/Zen 3 is 48 bytes/cycle. And it shouldn’t be as long as we hit the uop cache, which can deliver 64 bytes of instructions per cycle. Golden Cove’s pipeline is 6-wide, so we should get 48 bytes/cycle if instruction bandwidth isn’t a bottleneck. The test fills an array with those, puts a return (C3) at the end, and times how long it takes to execute in a loop. We wrote a test that measures instruction fetch bandwidth with 8 byte NOPs, specifically 0F 1F 84 00 00 00 00 00. That’s a notable improvement compared to Sunny Cove and Skylake, which could only fetch 16 bytes/cycle from their L1i caches and used 4-wide decoders. To feed those decoders, Intel has increased L1 instruction cache bandwidth to 32 bytes/cycle. If there’s a micro-op cache miss, Golden Cove has six instruction decoders. For comparison, Sunny Cove and Skylake could only fetch 6 micro-ops per cycle from their uop caches. Golden Cove can fetch 8 micro-ops per cycle from that cache, matching Zen in that respect. To accelerate this, Golden Cove gets a bigger 4K entry uop cache, up from 2.25K in Sunny Cove and 1.5K in Skylake. Once the branch predictor has told the CPU where the next instruction should be, it’s time to fetch it. Sunny Cove and Zen 2/3 in comparison are faster at returns, even at a lower clock – at least until their return stack overflows. But when calls go more than two deep, Golden Cove is rather slow at handling returns. There’s no clear jump up, even when we increased the number of call/return pairs to 128. Golden Cove’s return prediction behavior is strange. And of course, treat this diagram as a rough approximation, because testing is hard. We don’t have a board that allows AVX-512 instructions, and those instructions fault on Golden Cove, so unfortunately that won’t be covered. The rest comes from our own testing on an i9-12900K. Some of the our data comes from Intel’s Architecture Day presentation. To start, let’s look at Golden Cove from a mile up.
But in short, Golden Cove cores target peak performance. Finally, we’re going to skip introducing Alder Lake and Golden Cove, as other tech sites like Anandtech and Tom’s Hardware have already done that. In a few cases, we’ll show data from Skylake and AMD’s architectures to put Intel’s progress in perspective. Primarly, we’re going to compare Golden Cove to its direct predecessor, Sunny Cove, and use that as a basis for analyzing Intel’s design choices. Here, we’re going to deep dive ADL’s P-core architecture, Golden Cove. But I’m sure you all know that already from other sites that are able to do launch day reviews. For the first time since Skylake, Intel has launched a competitive desktop microarchitecture. Alder Lake (ADL) is the most exciting Intel launch in more than half a decade.
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